The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor device having a NAND-type memory structure.
A NAND-type memory cell structure is in use for almost all memory cells of the 4M bit level and higher, due to its advantage of easy high integration.
FIGS. 1 and 2 show the layout and equivalent circuit of the conventional NAND-type mask read-only-memory (ROM) cell structure.
Referring to FIG. 1, reference numeral 1 indicates an N.sup.+ active region used as the drain and source of a transistor, reference numeral 2 is an ion doped region having a depletion-type channel, reference numeral 3 is a region used as the gate electrode of the transistor and as connecting means inside the chip, reference numeral 4 is a contact hole region for interconnecting between the active region and a metal wiring, and between the metal wiring and a polysilicon layer, and reference numeral 5 is a metal wiring (bit-line) used as the connecting means.
As shown in FIGS. 1 and 2, in the conventional NAND-type mask ROM cell, two strings in parallel one of which is constituted by two string selection transistors and multi-cells numbering 4, 8, 16, 32 and so on which are serially connected between the bit-line contact and the ground line by equal spaces, are connected to one bit-line contact, to thereby constitute a basic unit in constructing the memory cell array. Here, one string comprises two transistors having an enhancement-type channel and depletion-type channel, respectively.
The conventional NAND-type mask ROM cell operates as follows, with reference to FIGS. 1, 2 and 3. Operation when cell A is turned on while cell B is turned off in FIGS. 1 and 2 will be explained.
First, in stand-by operation, the string selection line is at zero volts (0 V), the word-line is at Vcc level, and the bit line is floated. In read mode operation, when the string selection line 1 is Vcc level and the string selection line 2 is at 0 V, the string 1 is selected. In string 1, word-line 2 is switched to 0 V and the remaining word-lines thereof are switched to Vcc level, in order to select the cell transistor A of FIG. 2. At this time, the voltage of a bit line is determined as the selected cell, that is, a logic "low" or "high" depending on the state of cell A, is determined. In other words, logic "high" is selected when cell A is an enhancement-type NMOS, and logic "low" is selected when cell A is a depletion-type NMOS. A sense amplifier detects the bit-line voltage, thereby determining the data input/output (I/O).
FIGS. 4, 5 and 6 respectively show the layout, equivalent circuit thereof and the operation state of the memory cell structure where the ground selection line is added to the conventional NAND-type mask ROM cell so as to open the current path between word-line Vcc and ground in stand-by mode when a gate oxide film of cell transistor fails, i.e., when the oxide film is damaged.
Referring to the operations of the memory cell, the ground selection line is switched to "0 V" in stand-by mode, while the remaining operations are the same as those of the conventional NAND-type memory cell.
The occurrence of a polysilicon bridge resulting from impurity particles increases geometrically as the layout of the conventional NAND-type memory cell increases to ultra-high integration. Accordingly, the error correction code (ECC) or redundancy is provided so as to improve yield and reliability. However, a chip becomes defective due to poor stand-by current which has to be tested in the early stages of manufacturing when the string selection line and word-line or the word-line and ground selection line are electrically connected by the polysilicon bridge. Accordingly, the data correction effect by the ECC circuit or by a redundancy circuit cannot be obtained.